//---- File    	   : GP30Y_REG_A1.2.h
//---- Erstellt 	   : 05.02.2015
//---- Bearbeiter   : HG,SK
//---- Firma        : acam-messelectronic gmbh
//---- Projekt      : GP30Y
//----
//---- Description  : Declarations of register addresses and bitnumbers
// Changes in Version GP30Y_REG_A1.2.h: alternative constants added for compatibility with manual / some bit positions added

//---- Configuration Register ----------------------------------------------

#define CR_WD_DIS 0xC0	//---- Watchdog Disable
#define CR_PI_E2P 0xC1	//---- Pulse / EEPROM Interface
#define CR_GP_CTRL 0xC2 //---- General purpose control
#define CR_UART 0xC3	//---- UART Interface
#define CR_IEH 0xC4		//---- Interrupt & Error Handling
#define CR_CPM 0xC5		//---- Clock & Power Management
#define CR_MRG_TS 0xC6	//---- Measure rate generater and Task Sequencer
#define CR_TM 0xC7		//---- Temperature Measurement
#define CR_USM_PRC 0xC8 //---- Ultra Sonic Measurement
#define CR_USM_FRC 0xC9 //---- Ultra Sonic Measurement: Fire Receive Control
#define CR_USM_TOF 0xCA //---- Ultra Sonic Measurement: Time of Flight
#define CR_USM_AM 0xCB	//---- Ultra Sonic Measurement: Amplitude Measurement
#define CR_TRIM1 0xCC	//---- Trim parameters 1// USM Tuning Parameter
#define CR_TRIM2 0xCD	//---- Trim parameters 2// TDC Tuning Parameter
#define CR_TRIM3 0xCE	//---- Trim parameters 3// Analog Functions Tuning Parameter

//---- System Handling Register ---------------------------------------------

#define SHR_TOF_RATE 0xD0		   //---- System Handling: TOF_RATE
#define SHR_GPO 0xD3			   //---- System Handling: General Purpose Out
#define SHR_PI_NPULSE 0xD4		   //---- System Handling: Pulse Interface, Number of Pulses
#define SHR_PI_TPA 0xD5			   //---- System Handling: Pulse Interface, Distance of Pulses
#define SHR_PI_IU_TIME 0xD6		   //---- System Handling: Pulse Interface, Auto Update Time
#define SHR_PI_IU_NO 0xD7		   //---- System Handling: Pulse Interface, Number of Auto Updates
#define SHR_TOF_START_HIT_DLY 0xD8 //---- System Handling: Start Hit Delay
#define SHR_ZCD_LVL 0xD9		   //---- System Handling: ZCD Stored Value
#define SHR_ZCD_FHL_U 0xDA		   //---- Zero Cross Detection, First Hit Level Up
#define SHR_ZCD_FHL_D 0xDB		   //---- Zero Cross Detection, First Hit Level Down
#define SHR_CPU_REQ 0xDC		   //---- System Handling: CPU Requests
#define SHR_EXC 0xDD			   //---- System Handling: Execute Register
#define SHR_RC 0xDE				   //---- System Handling: Remote Control
#define SHR_FW_TRANS_EN 0xDF	   //---- System Handling: FW Transaction Enable

//---- Status & Result Register ---------------------------------------------

#define SRR_IRQ_FLAG 0xE0	 //---- Status & Result Register: IRQ Flags
#define SRR_ERR_FLG 0xE1	 //---- Status & Result Register: Error Flags
#define SRR_FEP_STF 0xE2	 //---- Status & Result Register: FEP Status Flag
#define SRR_GPI 0xE3		 //---- Status & Result Register: General Purpose In
#define SRR_HCC_VAL 0xE4	 //---- Status & Result Register: HCC Value
#define SRR_VCC_VAL 0xE5	 //---- Status & Result Register: VCC Value
#define SRR_TSV_HOUR 0xE6	 //---- Status & Result Register: Time Stamp Value, Hours
#define SRR_TSV_MIN_SEC 0xE7 //---- Status & Result Register: Time Stamp Value, Minutes & Seconds
#define SRR_TOF_CT 0xE8		 //---- Status & Result Register: TOF Cycle Time
#define SRR_TS_TIME 0xE9	 //---- Status & Result Register: Task Sequencer Time
#define SRR_MSC_STF 0xEA	 //---- Status & Result Register: Miscellaneous Status Flag
#define SRR_E2P_RD 0xEB		 //---- Status & Result Register: EEPROM Read Data
#define SRR_FWU_RNG 0xEC	 //---- Status & Result Register: FW User Range
#define SRR_FWU_REV 0xED	 //---- Status & Result Register: FW User Revision
#define SRR_FWA_REV 0xEE	 //---- Status & Result Register: FW Acam Revision
#define SRR_LSC_CV 0xEF		 //---- Status & Result Register: Low Speed Clock Count value

//================== Special Register Actions =====================================

#define SR_MCT_DIS 0x00000001	   //---- Measure Cycle Timer Disable		8'h8A
#define SR_MCT_EN 0x00000002	   //---- Measure Cycle Timer Enable		8'h8B
#define SR_PP_DIS 0x00000004	   //---- Post Processing Disable
#define SR_PP_EN 0x00000008		   //---- Post Processing Enable
#define SR_RP_DIS 0x00000010	   //---- Remote Processing Disable
#define SR_RP_RLS 0x00000020	   //---- Remote Processing Release
#define SR_BG_SPM 0x00000040	   //---- BG self pulsed
#define SR_BG_TPM 0x00000080	   //---- BG task pulsed
#define SR_CM_PM_NOK 0x00000100	   //---- CM & PM not OK
#define SR_CM_PM_OK 0x00000200	   //---- CM & PM OK
#define SR_NVM_TRIM_DIS 0x00000400 //---- NVM Trimming Disable
#define SR_NVM_TRIM_EN 0x00000800  //---- NVM Trimming Enable
#define SR_HSC_4MHZ 0x00000004	   //---- High Speed Clock / div 1 (4 MHz)
#define SR_HSC_8MHZ 0x00000008	   //---- High Speed Clock / div 1 (4 MHz)
#define SR_PI_DIS 0x00004000	   //---- Disable Pulse Interface
#define SR_PI_EN 0x00008000		   //---- Enable Pulse Interface

#define SR_PM_STORE 0x00010000	//---- CM_PM Store
#define SR_BM_STORE 0x00020000	//---- BM Store
#define SR_CM_RECALL 0x00040000 //---- CM Recall
#define SR_PM_RECALL 0x00080000 //---- PM Recall
#define SR_BM_RECALL 0x00100000 //---- BM Recall

#define SR_EH_CLR 0x00000001  //---- EH Clear
#define SR_FES_CLR 0x00000002 //---- FES Clear
#define SR_CFG_DONE 0x00000002
#define SR_TSC_CLR 0x00000004	   //---- TSC Clear
#define SR_TSV_UPD 0x00000008	   //---- TSV Update
#define SR_TOF_RATE_CLR 0x00000010 //---- TSV Update
#define SR_BG_REFRESH 0x00000020   //---- TSV Update
#define SR_UART_CRC_ON 0x00000020
#define SR_IF_CLR 0x00000040 //---- EH Clear
#define SR_WD_CLR 0x00000080 //---- WD Clear
#define SR_PI_UPD 0x00000100 //---- PI Update

#define SR_WD_DIS 0x48DBA399   //---- WD Disable
#define SR_STORE_EN 0xA0F5B8CA //---- Store Enable
#define SR_TEST_EN 0x6107C9DB  //---- Test Enable
#define SR_FW_RLS 0xABCD7654   //---- NV Ok

//================== Bit Numbers of CPU Request Register SHR_CPU_REQ =====================================
#define BNR_BLD_EXC 0 //---- CPU request boot loader execute
#define BNR_CHKSUM 1  //---- Request Checksum Generation
#define BNR_PP 2	  //---- Post Processing
#define BNR_EH 3	  //---- Error Handling// do not use
#define BNR_GPH 4	  //---- General Purpose Handling
#define BNR_FWI 5	  //---- Request Firmware Initialization

//================== Bit Numbers of SHR_GPO Register =====================================
#define BNR_GPO0_OUT 0 //---- General Purpose 0 Out
#define BNR_GPO1_OUT 1 //---- General Purpose 1 Out
#define BNR_GPO2_OUT 2 //---- General Purpose 2 Out
#define BNR_GPO3_OUT 3 //---- General Purpose 3 Out
#define BNR_GPO4_OUT 4 //---- General Purpose 4 Out
#define BNR_GPO5_OUT 5 //---- General Purpose 5 Out
#define BNR_GPO6_OUT 6 //---- General Purpose 6 Out

#define BNR_PI_OUT_FRC0 8  //---- Forces Low on Pulse Output
#define BNR_PI_OUT_FRC1 9  //---- Forces High on Pulse Output
#define BNR_PI_DIR_FRC0 10 //---- Forces Low on Pulse Direction
#define BNR_PI_DIR_FRC1 11 //---- Forces High on Pulse Direction
#define BNR_FWD1_CSE 12	   //---- FWD1 Checksum Error
#define BNR_FWD2_CSE 13	   //---- FWD2 Checksum Error
#define BNR_FWU_CSE 14	   //---- FWU Checksum Error
#define BNR_FWA_CSE 15	   //---- FWA Checksum Error

//================== Bit Numbers of Execute Register SHR_EXC ==================================
#define BNR_IF_CLR 0	   //---- Interrupt Flag Clear
#define BNR_EF_CLR 1	   //---- Error Flags Clear
#define BNR_FES_CLR 2	   //---- Frontend Status Clear
#define BNR_TSC_CLR 3	   //---- Timestamp Counter Clear
#define BNR_TSV_UPD 4	   //---- Timestamp Value Update
#define BNR_PI_UPD 5	   //---- Pulse Interface Update
#define BNR_BG_REFRESH 6   //---- Bandgap Refresh
#define BNR_E2P_CLR 7	   //---- EEPROM Clear
#define BNR_TOF_RATE_CLR 8 //---- TOF Rate Clear
#define BNR_ZCC_RNG_CLR 9  //---- Zero Cross Calibration: Range Clear
#define BNR_FW_IRQ_S 10	   //---- Firmware Interrupt Request, synchronized
#define BNR_FW_IRQ 11	   //---- Firmware Interrupt Request
#define BNR_COM_REQ_CLR 12 //---- Communication Request Clear
#define BNR_GPR_REQ_CLR 13 //---- General Purpose Request Clear
#define BNR_GPH_TRIG 14	   //---- General Purpose Trigger (via Task Seq.)
#define BNR_BUH_TRIG 15	   //---- Backup Handling Trigger (via Task Seq.) // Do not use !

//================== some Bit Numbers of various Config Registers =====================================
#define BNR_PI_EN 8		 //---- Pulse Interface Enable, register CR_PI_E2P
#define BNR_HS_CLK_DIV 8 //---- High Speed Clock divider=HS_CLK_SEL, 4MHz (0) or 8MHz (1), register CR_CPM
#define BNR_HS_CLK_SEL 8 //---- HS_CLK_SEL, 4MHz (0) or 8MHz (1), register CR_CPM
#define BNR_CRC_MODE 13	 //---- UART CRC operating with default (0) or with configured settings (1), register CR_UART
#define BNR_BLD_CS 31	 //---- Checksum Execution after Bootloader enabled (1), register CR_IEH

// Configuration register bits for Temperature Measurement in CR_TM
#define BNR_TM_PORT_NO 16  //---- Number of ports (for external measurement)
#define BNR_TM_EXT_MODE 15 //---- 2 or 4 wire (Temperature extern mode)
#define BNR_TM_MODE_1 14   //---- Temperature Measurement Mode: If 1 then toggling
#define BNR_TM_MODE_0 13   //---- Temperature Measurement Mode

//================== Bit Numbers of FEP Status Flag Register SRR_FEP_STF =====================================
#define BNR_HCC_UPD 0  //---- High Speed Clock Calibration Update
#define BNR_TM_UPD 1   //---- Temperature Update
#define BNR_TM_MODE 2  //---- Temperature Measurement Mode
#define BNR_TM_ST 3	   //---- Temperature Measurement Subtask
#define BNR_US_U_UPD 4 //---- US Up Update
#define BNR_US_D_UPD 5 //---- US Down Update
#define BNR_TOF_UPD 6  //---- TOF Update
#define BNR_TOF_EDGE 7 //---- TOF Measurement edge
#define BNR_AM_UPD 8   //---- AM Update
#define BNR_AMC_UPD 9  //---- AMC Update

//================== Bit Numbers of Interrupt Flags (SRR_IRQ_FLAG) Register ==========================
#define BNR_ERR_FLAG 7 //---- 1 when at least one error flag is set

#define BNR_SRR_FW_IRQ 5   //---- Firmware Interrupt Request
#define BNR_SRR_FW_IRQ_S 4 //---- Firmware Interrupt Request, synchronized with task sequencer
#define BNR_CHKSUM_FNS 3   //---- Checksum Subroutine Finished
#define BNR_BLD_FNS 2	   //---- Bootloader Finished

//================== Bit Numbers of Error Flags (SRR_ERR_FLAG) Register ==========================
#define BNR_CS_FWA_ERR 15  //---- FWA checksum error
#define BNR_CS_FWU_ERR 14  //---- FWU checksum error
#define BNR_CS_FWD2_ERR 13 //---- FWD2 checksum error
#define BNR_CS_FWD1_ERR 12 //---- FWD1 checksum error

#define BNR_E2P_ACK_ERR 10 //---- EEPROM Acknowledge Error
#define BNR_TSQ_TMO 9	   //---- Task Sequencer timeout
#define BNR_TM_SQC_TMO 8   //---- Temperature sequence timeout
#define BNR_USM_SQC_TMO 7  //---- Ultrasonic sequence timeout
#define BNR_LBD_ERR 6	   //---- Low Battery Detect Error
#define BNR_ZCC_ERR 5	   //---- Zero Cross Calibration Error
#define BNR_TM_SC_ERR 4	   //---- Temperature Measurement Short Circuit Error
#define BNR_TM_OC_ERR 3	   //---- Temperature Measurement Open Circuit Error
#define BNR_AM_TMO 2	   //---- Amplitude Measurement Timeout
#define BNR_TOF_TMO 1	   //---- TOF Timeout
#define BNR_TDC_TMO 0	   //---- TDC Timeout

//================== Bit Numbers of General Purpose In (SRR_GPI) Register ==========================
#define BNR_LS_CLK_S 11 //---- Low speed clock, synchronized to CPU clock
#define BNR_NVM_RDY 10	//---- NVRAM ready
#define BNR_UART_SEL 9	//---- UART Select
#define BNR_LP_MODE 8	//---- Low Power Mode

#define BNR_GPI6_IN 6 //---- GPI 6 in
#define BNR_GPI5_IN 5 //---- GPI 5 in
#define BNR_GPI4_IN 4 //---- GPI 4 in
#define BNR_GPI3_IN 3 //---- GPI 3 in
#define BNR_GPI2_IN 2 //---- GPI 2 in
#define BNR_GPI1_IN 1 //---- GPI 1 in
#define BNR_GPI0_IN 0 //---- GPI 0 in

//================== Bit Numbers of Miscellaneous Status Flag Register SRR_MSC_STF =============================
#define BNR_WD_DIS 15 //---- Watchdog Disabled

#define BNR_E2P_ACK 13 //---- EEPROM Acknowledge
#define BNR_GPR_REQ 5  //---- General purpose Request by remote interface
#define BNR_COM_REQ 4  //---- Communication Request by remote interface

//-----------------------------------------------------------------------------------------------------
